The demand for semiconductor integrated circuit (IC) devices such as computer chips with high circuit speed and high circuit density requires the downward scaling of feature sizes in ultra-large scale integration (ULSI) and very-large scale integration (VLSI) structures. The trend to smaller device sizes and increased circuit density requires decreasing the dimensions of interconnect features and increasing their density. An interconnect feature is a feature such as a via or trench formed in a dielectric substrate which is then filled with metal, typically copper, to render the interconnect electrically conductive. Copper has been introduced to replace aluminum to form the connection lines and interconnects in semiconductor substrates. Copper, having better conductivity than any metal except silver, is the metal of choice since copper metallization allows for smaller features and uses less energy to pass electricity. In damascene processing, interconnect features of semiconductor IC devices are metallized using electrolytic copper deposition.
In the context of semiconductor integrated circuit device manufacture, substrates include patterned dielectric films on semiconductor wafer or chip substrates such as, for example, SiO2 or low-K dielectric films on silicon or silicon-germanium. Typically, a wafer has layers of integrated circuitry, e.g., processors, programmable devices, memory devices, and the like, built into one or more layers of dielectric on a semiconductor substrate. Integrated circuit (IC) devices have been manufactured to contain sub-micron vias and trenches that form electrical connections between layers of interconnect structure (via) and between devices (trench). These features typically have dimensions on the order of about 200 nanometers or less, such as about 150 nanometers, less than about 100 nanometers, or even less than about 50 nanometers.
The use of copper has introduced a number of requirements into the IC manufacturing process. First, copper atoms have a tendency to diffuse into the semiconductor's junctions, such as by current-induced migration, thereby disturbing their electrical characteristics. To combat this occurrence, a barrier layer, such as titanium nitride, tantalum, tantalum nitride, or other layers as are known in the art, is applied to the patterned dielectric prior to the copper metallization that involves copper seed layer deposition (typically by PVD process) followed by electrolytic copper deposition to achieve void-free filling. As the architecture of ICs continues to shrink, this requirement proves to be increasingly difficult to satisfy.
One conventional semiconductor manufacturing process is the copper damascene system. Specifically, this system begins by etching the circuit architecture into the substrate's dielectric material. The architecture is comprised of a combination of the aforementioned trenches and vias. Next, a barrier layer is laid over the dielectric to prevent diffusion of the subsequently applied copper layer into the substrate's junctions, followed by physical or chemical vapor deposition of a copper seed layer to provide electrical conductivity for a sequential electrochemical process. Copper to fill into the vias and trenches on substrates can be deposited by plating (such as electroless or electrolytic), sputtering, plasma vapor deposition (PVD), and chemical vapor deposition (CVD). It is generally recognized that electrochemical deposition is the best method to apply Cu since it is more economical than other deposition methods and can flawlessly fill into the interconnect features (often called “bottom up” growth or superfilling). After the copper layer has been deposited, excess copper is removed from the facial plane of the dielectric by chemical mechanical polishing, leaving copper in only the etched interconnect features of the dielectric. Subsequent layers are produced similarly before assembly into the final semiconductor package.
Copper plating methods must meet the stringent requirements of the semiconductor industry. For example, copper deposits must be uniform and capable of flawlessly filling the small interconnect features of the device, for example, with openings of 100 nm or smaller.
Electrolytic copper systems have been developed which rely on so-called “superfilling” or “bottom-up growth” to deposit Cu into various aspect ratio features. Superfilling involves filling a feature from the bottom up, rather than at an equal rate on all its surfaces, to avoid seams and pinching off that can result in voiding. Multi-part systems consisting of a suppressor and an accelerator as additives have been developed for superfilling, as in Too et al., U.S. Pat. No. 6,776,893, which discloses sulfide-based compounds for accelerating and a polyether-based compound for suppressing. Further improvements in bottom up filling are described in Paneccasio U.S. Pat. Nos. 7,303,992 and 7,815,786 which describe suppressors in which a polyether comprising a combination of propylene oxide (PO) and ethylene oxide (EO) is bonded to a nitrogen-containing species. As the result of momentum of bottom-up growth, the Cu deposit is thicker on the areas of interconnect features than on the field area that does not have features. These overgrowth regions are commonly called overplating, overburden, mounding, bumps, or humps. Smaller features generate higher overplating humps due to faster superfill speed. Larger features generally fill slower, which can lead to formation of dimples (also called underplate or underplating), and thus requires additional copper plating to achieve complete planarity. Additional copper plating to correct underplating may further exacerbate overplating. Overplating poses challenges for later chemical and mechanical polishing processes that planarize the Cu surface. A third organic additive called a “leveler” is typically used to address overgrowth and other issues, as in Commander et al., U.S. Pub. No. 2003/0168343 and Paneccasio et al. U.S. Pat. No. 8,608,933.
As chip architecture gets smaller, with interconnects having openings on the order of 100 nm and smaller through which Cu must grow to fill the interconnects, there is a need for enhanced bottom-up speed. That is, the Cu must fill “faster” in the sense that the rate of vertical growth from the feature bottom must be substantially greater than the rate of growth on the rest of areas, and even more so than in conventional superfilling of larger interconnects.
In addition to superfilling and overplating issues, micro-defects may form when electrodepositing Cu for filling interconnect features. One defect that can occur is the formation of internal voids inside the features. As Cu is deposited on the feature side walls and top entry of the feature, deposition on the side walls and entrance to the feature can pinch off and thereby close access to the depths of the feature especially with features which are small (e.g., <100 nm) and/or which have a high aspect ratio (depth:width) if the bottom-up growth rate is not fast enough. Smaller feature size or higher aspect ratio generally requires faster bottom-up speed to avoid pinching off. Moreover, smaller size or higher aspect ratio features tend to have thinner seed coverage on the sidewall and bottom of a via/trench where voids can also be produced due to insufficient copper growth in these areas. An internal void can interfere with electrical connectivity through the feature.
Microvoids are another type of defect which can form during or after electrolytic Cu deposition due to abnormal Cu growth or grain recrystallization that happens after Cu plating, such as, for example, during high temperature anneal steps. U.S. Pub. No. 2003/0168343 discloses a method of using an electrolytic deposition chemistry comprising a leveler additive that increases the overall impurity (Cl, S, C, O, N) content of copper metallization in interconnect features.
Substantial improvements have been made in damascene copper plating of submicron features of semiconductor integrated circuit devices. For example the additives and plating compositions described in the aforesaid Commander and Paneccasio patent documents have represented significant advances in this area of technology.
Other features of microelectronic devices to be filled with copper include Through Silicon Vias. Through silicon vias are critical components of three-dimensional integrated circuits, and they can be found in RF devices, MEMs, CMOS image sensors, Flash, DRAM, SRAM memories, analog devices, and logic devices.
The dimensions of through silicon vias (TSVs) are several orders of magnitude larger than the submicron interconnects, but present their own set of problems in gap filling. The depth of a TSV depends on the via type (via first or via last), and the application. Via depth can vary from 3 to 500 microns, e.g., from 20 microns to 500 microns, typically between about 30 and about 250 microns, or between about 50 microns and about 250 microns. Via openings in TSV have had entry dimensions, such as the diameter, on the order of between about 200 nm to about 200 microns, typically between about 25 microns and about 75 microns.
Filling large size through silicon via in commercially practicable durations is a barrier to the commercial feasibility of devices employing TSVs. Experimental data obtained to date suggest that conventional electrolytic copper deposition methods employing compositions appropriate for damascene metallization (i.e., the composition comprises the three component superfilling additives including accelerator, suppressor, and leveler) are current density limited (such as about 0.10 A/dm2. or less to get defect-free fill) and may require plating durations as long as 20 hours to completely metallize large dimension (e.g., greater than 50 micron diameter openings) through silicon via.
Arana et al. US 2007/0001266 and Lane et al. U.S. Pat. No. 7,081,408 describe various methods for filling through silicon vias.
Copper plating is also known from, e.g., Eilert (U.S. Pat. No. 7,111,149); Rumer et al. (U.S. Pat. No. 6,924,551); Shi et al. (U.S. Pub. No. 2007/0085198); Ramanathan et al. (U.S. Pub. No. 2007/0117348) Heck et al. (U.S. Pub. No. 2006/0264029); Williams et al. (U.S. Pub. No. 2006/0273455); Rangel (U.S. Pub. No. 2006/0278979); and Savastiouk et al. (U.S. Pub. No. 2005/0136635). But none of these references, which relate to through silicon via architectures and methods, disclose applicable copper metallization chemistries or plating durations sufficient to fill through silicon via features.
The additives, compositions and electrolytic plating processes described in Richardson et al. US 2013/0199935 represent a significant advance in the art of filling through silicon vias. In that application, the TSVs are filled from a plating solution that contains a source of copper ions, chloride ion, and a leveler selected from the group consisting of a quaternized dipyridyl compound and a reaction product of benzyl chloride with hydroxyethylpolyethyleneimine.